Contact us    Access Map    Site map  Altis The activity of Altis Technologies Customers & markets Altis offer R & D The industrial site Altis & quality Altis & the environment Altis' news Employment Press Portfolio .25 µm .18 µm .13 µm TECHNOLOGIES  .13 µm Print Advanced features P-Silicon, non-Epi Shallow Trench isolation Dual work function Single poly, 8 layers of cop dual damascene metallization Planarized passivation and interlevel dielectric Process options: Dual Gate Ox, Poly/Implanted resistors, Metal to metal and Poly/N-well capacitors, Hi/Lo Vt N and P FETs, Thick aluminum Devices Options: MIMCAP, Inductors, eDRAM module Wire Bond or Flip-chip terminals The planarized passivation combined with number of metal layers enable the most efficient use of semiconductor area through higher densities and denser integration The devices options bring new solutions to the circuit designers giving better efficiency and higher flexibility to the design Highlights ALTIS SEMICONDUCTOR 0.13µm Technology is an advanced high-yield process based on industry standard 0.13µm-ground-rules process. This technology is a key element of the ALTIS SEMICONDUCTOR technology roadmap. This 0.13µm process is highly flexible and is optimized for low leakage/high density applications like wireless and consumer applications. It enables to address a wide range of SoC, digital, analogy, mixed signal and RF applications. Numerous process options have been taylored to specific customer requirements. The ALTIS SEMICONDUCTOR 0.13µm Technology has been successfully released on February 2002 and is in full production for major market players. This 0.13µm technology is the second generation of copper interconnect technology, which takes full benefit of the long manufacturing experience accumulated on the previous copper technology. This allows for new products to expect fast time-to-market and efficient yield learning. The 0.13µm technology manufacturing is performed in a high quality manufacturing line, which allows reaching best quality and reliability levels. 0.13 µm TECHNOLOGY KEY FEATURE  Technologie  0.13µm  Lithography  0.12µm Deep UV - Phase shifting  Ldrawn  0.092µm  Leff  0.077µm  Gate Oxide Thickness  22 A  Isolation  Shallow Trench Isolation  Polysilicon  Single poly  Intermetal dielectric  Oxide/FSG  Via fill  W for M1 to M8  Poly/Metal layers  1Poly 3 to 8 Metal (Cu)  Poly/Metal pitch  M0 - Poly  0.48µm  M1 - Metal 1  0.32  M2 to M6  0.40µm  Process Options  Dual Gate Ox (3.3 Volts I/O)  High Vt/Low Vt N and P Fets  Meta to Metal capacitors -MIMCAP-  Poly/N-Well capacitors 0.13 µm TECHNOLOGY CIRCUIT KEY CARACTERISTICS  Supply Voltage      1.2 - 1.5 Volts  I/O Voltage        3.3/2.5/1.8/1.5 Volts  Gate  Density      > 180 K row gates per mm_  Delay 18.5 ps -NAND2, FO2 , nominal-  Power                   Typical 9 nW/gate/MHz  Transistors  Regular MOS  Treshhold voltages  Vth  0.37 / -0.32 V  Saturation currents  Idsat = Ion  500 / 210 uA/µm  Leakage currents  Ileak = Ioff  < 200 pA / µm  Low-power MOS  Treshhold voltages  Vth  0.55 / -0.44 V  Saturation currents  Idsat = Ion  350 / 150 uA/µm  Leakage currents  Ileak = Ioff  < 10 / 10 pA / µm  Zero Vt nFET  Treshhold voltages  Vth Vtsat @min L  0.26 / -0.24 V  Saturation currents  Idsat = Ion  650 / 290 uA/µm  Leakage currents  Ileak = Ioff  < 2 / 2 nA / µm  Ultra low Vt nFET  Treshhold voltages  Vth Vtsat @min L  0.29 / -0.245 V  Saturation currents  Idsat = Ion  550 / 240 uA/µm  Leakage currents  Ileak = Ioff  < 2 / 2 nA / µm  Analog transistor  Treshhold voltages  Vth  0.42 / -0.41 V  Saturation currents  Idsat = Ion  480 / 140 uA/µm  Leakage currents  Ileak = Ioff  20 / 20 pA/µm  6TSRAM  Std  Cell Area    2.48 µm²  Dense  Cell Area    2.28 µm²  DRAM    Cell Area    0.31 µm²  Resistors  Diffusion    N-Type  76 ? / sq  Poly    P-Type  310 ? / sq  Capacitors   MIMCAP :    Std 2.0 fF/µm²  Inductors        yes ALTIS SEMICONDUCTOR - copyright 2004