Contact us    Access Map    Site map  Altis The activity of Altis Technologies Customers & markets Altis offer R & D The industrial site Altis & quality Altis & the environment Altis' news Employment Press Portfolio .25 µm .18 µm .13 µm TECHNOLOGIES  .18 µm Print Advanced features P-Silicon, non-Epi Shallow Trench isolation Dual work function Single Poly, 6 layers of Copper dual damascene metallization Planarized passivation and interlevel dielectric Process options : Dual Gate Ox, Poly/Implanted resistors, Metal to metal and Poly/N-well capacitors, Hi/Lo Vt N and P FETs, Thick alu Devices Options : MIMCAP, Inductors, substrate Bipolar PNP, eDRAM Wire Bond or Flip-chip terminals Highlights ALTIS SEMICONDUCTOR 0.18µm Technology is an advanced high-yield process based on industry standard 0.18µm-ground-rules process relying on narrow pitch copper interconnects. This process is a key element of the ALTIS SEMICONDUCTOR technology roadmap. This 0.18µm-ground-rules process enables to address a wide range of digital, analog, mixed signal and RF applications. A wide range of process options allows bringing dedicated solutions to specific customer requirements. ALTIS SEMICONDUCTOR has been successfully in volume production for major market players on that technology since July 2000. This long experience allows for new products to expect fast time-to-market and efficient yield learning. The 0.18µm technology manufacturing is performed in a high quality manufacturing line, achieving top quality and reliability levels. 0.18 µm TECHNOLOGY KEY FEATURE  Technologie  0.18µm  Lithography  0.18µm Deep UV  Ldrawn  0.15µm  Leff  0.11µm  Gate Oxide Thickness  35 A (1.8 Volts)  68 A (3.3 Volts I/O)  Isolation  Shallow Trench Isolation  Polysilicon  Single layer  Intermetal dielectric  SiO2  Via fill  Cu for M1 to M6  Poly/Metal layers  1Poly 2 to 6 Metal (Cu)  Poly/Metal pitch  M0 - Poly 0.60µm  M1 - Metal 1 0.44µm  M2 to M6 0.56µm  Process Options  Dual Gate Ox (3.3 Volts I/O)  high Vt/Low Vt N and P Fets  Meta to Metal Capacitors-MIMCAP  Poly/N-Well capacitors 0.18 µm TECHNOLOGY CIRCUIT KEY CARACTERISTICS  Supply Voltage       1.8 Volts  I/O Voltage        3.3/2.5/1.5 Volts  Gate  Density       > 120 K raw gates per mm²  Delay 33 ps -NAND2, FO2 , nominal-  Power  Typical 20nW/gate/MHz  Transistors  High performance MOS  Treshhold voltages  Vth  0.43/ -0.38 V  Saturation currents  Idsat = Ion  600/ -260 uA/µm  Leakage currents  Ileak = Ioff  0.5 nA / µm  Low-power MOS  Treshhold voltages  Vth  0.56 / -0.495 V  Saturation currents  Idsat = Ion  500 / -210 uA/µm  Leakage currents  Ileak = Ioff  15 pA / µm  3.3 V I/O transistors  Treshhold voltages  Vth  0.64 / -0.65 V  Saturation currents  Idsat = Ion  550 / -235 uA/µm  Leakage currents  Ileak = Ioff  5 pA/µm  Analog transistors  Treshhold voltages  Vth  0.42 / -0.37 V  Saturation currents  Idsat = Ion  450 / -200 uA/µm  Leakage currents  Ileak = Ioff   8 / 10 pA/µm  Substrate pnp (ß = 1.9)    VEA  25 V  6TSRAM  Cell Area    Standard  4.96 µm²    Dense  3.67 µm²  DRAM  Cell Area      0.56 µm²  Resistors  Diffusion    N-Type   75 ? / sq    P-Type   112 ? / sq  Poly    N-Type  350 ? / sq    P-Type  270 ? / sq  Capacitors  MIMCAP :    Std  1.0fF/µm²  Poly-Substrate Capacitor    Thin Ox  7.76 fF/µm    Thick Ox  4.37 fF/µm ALTIS SEMICONDUCTOR - copyright 2004