Contact us    Access Map    Site map  Altis The activity of Altis Technologies Customers & markets Altis offer R & D The industrial site Altis & quality Altis & the environment Altis' news Employment Press Portfolio .25 µm .18 µm .13 µm TECHNOLOGIES  .25 µm Print Advanced features P-Epi on P+ substrate Shallow Trench isolation Dual work function Single Poly, 6 layers of Alu metal process Planarized passivation and interlevel dielectric Process options : Dual Gate Ox, Poly/Implanted resistors, Metal to metal and Poly/N-well capacitors, Hi/Lo Vt N and P FETs, Thick alu Devices Options : MIMCAP, Inductors, 5V Transistor Wire Bond or Flip-chip terminals Highlights ALTIS SEMICONDUCTOR 0.25µm Technology is an robust high-yield process based on industry standard 0.25µm-ground-rules process. This process is a key element of the ALTIS SEMICONDUCTOR technology roadmap. This 0.25µm-ground-rules process enables to address a wide range of digital, analog, mixed signal and RF applications using industry standard EDA tools and the numerous process options allow to bring dedicated solutions to specific requirements. ALTIS SEMICONDUCTOR has been successfully in volume production (computer peripherals, image, video, wireless, wireline and automotive) for major market players on that technology since 1998. This allows for new products to expect fast time-to-market and efficient yield learning. The 0.25µm technology manufacturing is performed in a high quality manufacturing line, achieving top quality and reliability levels. 0.25 µm TECHNOLOGY KEY FEATURE  Technologie  0.25µm  Lithography  0.25µm - Deep UV  Ldrawn  0.24µm  Leff  0.18µm  Gate Oxide Thickness  50 A ( 2.5 Volts )  70 A ( 3.3 Volts I/O)  Isolation  Shallow Trench Isolation  Polysilicon  Single layer  Intermetal dielectric  SiO2  Via fill  W for M1 to M6  Poly/Metal layers  1Poly 2 to 6 Metal (Alu)  Poly/Metal pitch  M0 - Poly 0.60µm  M1 - Metal 1 0.64µm  M2 to M6 0.80µm  Process Options  Dual Gate Ox (3.3 Volts I/O)  High Vt/Low Vt N and P Fets  Meta to Metal capacitors -MIMCAP-  Poly/N-Well capacitors  4µm-Thickness last Metal (alu) 0.25 µm TECHNOLOGY CIRCUIT KEY CARACTERISTICS  Supply Voltage      2.5 Volts  I/O Voltage        2.5/1.8 Volts  Gate  Density       > 40 K raw gates per mm²  Delay 50 ps -NAND2, FO2 , nominal-  Power  Typical 40nW/gate/MHz  Transistors  High performance MOS  Treshhold voltages  Vth  (Vt sat ) 0.335 / -0.266 V  Saturation currents  Idsat = Ion  639 / 338 uA/µm  Leakage currents  Ileak = Ioff  28 / 270 pA/µm  Regular MOS  Treshhold voltages  Vth  ( vt sat ) 0.440 / -0.405 V  Saturation currents  Idsat = Ion  595 / 280 uA/µm  Leakage currents  Ileak = Ioff  2.3 / 10 pA/µm  Low-power MOS  Treshhold voltages  Vth  ( vt sat ) 0.545 / -0.529 V  Saturation currents  Idsat = Ion  548 / 229 uA/µm  Leakage currents  Ileak = Ioff  0.24 / 1.1 pA/µm  Zero Vt nFET  Treshhold voltages  Vth Vtsat @min L  -0.07 V  Saturation currents  Idsat = Ion  592 uA/µm  3.3 V I/O transistors (& Analog Tx)  Treshhold voltages  Vth  (Vt sat ) 0.425 / -0.460 V  Saturation currents  Idsat = Ion  580 / 285 uA/µm  Leakage currents  Ileak = Ioff  2 / 1.7 pA/µm  5 Volts transistors  Treshhold voltages  Vth  0.970 / - 1.035 V  Saturation currents  Idsat = Ion  505 / - 190 uA/µm  Leakage currents  Ileak = Ioff   Nom 1.5 / -3 , max @ 25°c 15 / -15  Substrate pnp (ß = 1.9)    VEA  Beta 3.9 , VCE 14V  6TSRAM  Cell Area    Standard  10µm²    Dense   7.5µm²  Resistors  Diffusion    N-Type  63 ? / sq    P-Type  100 ? / sq  Poly    N-Type   210 - 3600 ? / sq  Capacitors  BR Capacitor      4.8fF/µm²  MIMCAP :    Std  0.7fF/µm² +/- 10%   SIN MIMCAP  2.0 fF/µm²  Inductors        Q = 15 -20 @ 1-2 GHz ALTIS SEMICONDUCTOR - copyright 2004