|
|
With geometries becoming finer and finer, SoC designers face complex challenges in meeting a timely anddefect-free tape-out.
|
Altis SC is the only pure-play foundry in Europe to offer acomplete in-house SoC engineering support enabling a seamless and successful design-to-silicon transition.
 The Foundry Engineering
Altis SC is the pure-play foundry that has invented the "Foundry Engineering" Concept. Altis SC has the vocation to be the competence center for customizing the perfect match between your IC design and our technologies. From before-silicon up to volume production, an adapted service offer is at your disposal at every stage of your project
We developed state-of-the-industry engineering support infrastructures and capabilities, to leverage your design into reliable, top quality and high yielding silicon.
Libraries and IP:enabling sucessful design-to-silicon transition
Accurate and reliable models and process characterization data are key elements for first silicon success. Altis SC provides design elements and libraries compatible to industry standard design flows.
Our strategy is to enhance and maintain a broad and high quality portfolio of proven IP cores through partners meeting our selection criteria.
Our foundry-compatible logic and mixed-signal processes are proven for high-volume production. SoC designs are further supported by a variety of modular embedded memory and RF options.
Our Concept:100% yield@1st-silicon
Using our wide experience in semiconductor design-to-process interaction analysis, we collaborate with design teams in order to widen process windows and
improve yields.
In-depth analysis of defect density parameters allows to identify optimum schemes for memory redundancy architectures. Logic parts of the chips can be enhanced for yield by using optimized layout rules and feature redundancy (i.e. by interconnect wiring rules, redundant vias, ...).
Design-for-Test
ALTIS SC test engineering lab can provide support for test sequence development and optimization. Our experts significantly reduce test cost through high level parallelism by advanced probe card design.
|
 |
SOC ENGINEERED FOR MANUFACTURABILITY: TIME TO DESIGN